Picobus - timing information
This page expands on our basic picobus information page,
by illustrating the timing of the bus.
Typically the "Qn" timing on the Picobus will be handled by the
scanning microprocessor. The scanning microprocessor may
generate the Q0/Q1/Q2/Q3 signals directly, but more likely there
will be an external counter or decoder run by the microprocessor.
While only 4 lines are shown on picobus, the timing allows for
up to 10 multiplexed signals total. A typical circuit is below:
Note: This circuit is presented as a
typical example only and is not mandatory
|Typical PicoBus multiplex generator circuit|
The typical timing involves the microprocessor issuing a clock
pulse once every multiplex period. Most implementations will have
the Reset signal pulsed once every 'n' multiplex periods. The data
being sent out to multiplex devices (as distinct from the data being
read back from these devices) is changed just prior to the new
clock edge. For this reason, it is most suitable to have some port
lines (for instance and preferentially DEV) as outputs, and others
(for instance and preferentially DOD) as inputs if required.
A typical timing diagram is shown below.
|Typical PicoBus multiplex timing
One of the real advantages of Picobus, is that even though
it includes power, ground, and i2c signals, the multiplexing
leaves enough signals available so that "8 wide" devices
such a DIP-switch can still be connected.
This page had a Maintenance update: 23 April 2013